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regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is n ecessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein.
f-ztat microcomputer on-board programming application note hitachi micro systems, incorporated joe brennan 5/16/95
notice when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications.
preface this application note describes on-board programming of f-ztat? microcomputers (h8/538f, h8/3434f, h8/3334yf, h8/3048f) which have on-chip flash memory that can be programmed after mounting on the board, and also on-board programming tools. it has been prepared as a reference guide to on-board programming for users engaged in system design. the circuits in this application note are included to illustrate examples of on-board programming, and their contents are not guaranteed. be sure to check the operation of any circuits before actual use. note: *1. f-ztat (flexible-zero turn around time) is a trademark of hitachi, ltd. organization of f-ztat microcomputer on-board programming application note section 1 f-ztat microcomputer overview ? introduces the complete range of f-ztat microcomputer products and outlines their features. ? describes the two on-board programming modes (boot mode and user program mode). section 2 on-board programming tools ? describes the control aspects of hitachis tools for facilitating on-board programming: the adapter board (providing hardware support during on-board programming), and pc interface software (providing software support during on-board programming). section 3 examples of use with user machine ? describes the type of circuitry required in the user machine to conduct on-board programming/erasure for an f-ztat microcomputer using hitachis on-board programming tools (adapter board and pc interface software). section 4 on-board programming methods ? describes the requirements for f-ztat microcomputer programming/erasure using hitachis on-board programming tools, and the operating procedure in each on-board programming mode.
contents section 1 f-ztat microcomputer overview .............................................................. 1 1.1 f-ztat microcomputer product introduction .................................................................. 1 1.2 on-board programming modes ......................................................................................... 2 1.2.1 boot mode............................................................................................................. 2 1.2.2 user program mode .............................................................................................. 3 1.2.3 flash memory emulation by ram ...................................................................... 7 1.2.4 program voltage (vpp = 12 v) on/off, and reset signal timing ...................... 15 section 2 on-board programming tools ...................................................................... 17 2.1 adapter board ............................................................................................................... ..... 17 2.2 hardware configuration..................................................................................................... 1 9 2.2.1 rs-232c interface................................................................................................. 21 2.2.2 switch unit (program mode switching and vcc/vpp on/off)............................ 24 2.2.3 on-board programming power-on timing unit.................................................. 27 2.2.4 power unit ............................................................................................................ 29 2.3 pc interface software ....................................................................................................... .30 2.3.1 functions ............................................................................................................... 30 2.3.2 pc i/f software display on host machine ........................................................... 32 2.3.3 pc i/f software transfer processing.................................................................... 34 2.3.4 pc i/f software program/erase control program ................................................ 46 section 3 examples of use with user machine .......................................................... 61 3.1 user machine for on-board programming........................................................................ 61 3.1.1 user machine connector ...................................................................................... 62 3.1.2 reset circuit.......................................................................................................... 63 3.1.3 reverse current prevention circuit ...................................................................... 64 3.2 sci switching circuit example ......................................................................................... 65 3.2.1 sci switching circuit configuration.................................................................... 65 3.2.2 sci switching circuit operation .......................................................................... 66 3.3 reset buffer circuit example ............................................................................................ 69 3.3.1 reset buffer circuit operation.............................................................................. 70 section 4 on-board programming methods ................................................................ 72 4.1 on-board programming methods ...................................................................................... 72 4.1.1 on-board programming preparation .................................................................... 72 4.1.2 programming in boot mode.................................................................................. 73 4.1.3 user program mode preparation........................................................................... 76 4.1.4 programming in user program mode ................................................................... 81
4.1.5 operation method for flash memory emulation by ram .................................. 83 figures figure 1.1 boot mode overview .............................................................................................. 3 figure 1.2 user program mode overview................................................................................ 4 figure 1.3 block partitioning of h8/538f on-chip flash memory......................................... 5 figure 1.4 block partitioning of h8/3434f and h8/3334yf on-chip flash memory............ 6 figure 1.5 block partitioning of h8/3048f on-chip flash memory....................................... 7 figure 1.6 preparation for flash memory emulation by ram................................................ 8 figure 1.7 user program mode startup.................................................................................... 9 figure 1.8 program/erase control program startup.................................................................. 10 figure 1.9 application program startup ................................................................................... 11 figure 1.10 writing to flash memory ........................................................................................ 12 figure 1.11 ram overlap operation example (addresses h'ec00Ch'ecff) ......................... 14 figure 1.12 program voltage (vpp = 12 v) on/off timing...................................................... 16 figure 2.1 adapter board........................................................................................................ .. 17 figure 2.2 adapter board configuration .................................................................................. 20 figure 2.3 rs-232c interface circuit configuration example ................................................ 21 figure 2.4 connecting the adapter board to an ibm pc ......................................................... 22 figure 2.5 example of rs-232c interface circuit configuration............................................ 23 figure 2.6 programming mode switching................................................................................ 24 figure 2.7 transfer switch...................................................................................................... .. 25 figure 2.8 power switch ......................................................................................................... .. 25 figure 2.9 power supply switching jumper switch ................................................................ 26 figure 2.10 timing control circuit configuration..................................................................... 27 figure 2.11 adapter board 12-v on/off and reset signal control timing.............................. 28 figure 2.12 power unit circuit configuration ........................................................................... 29 figure 2.13 user machine to host machine connection............................................................ 31 figure 2.14 transfer processing in each pc i/f software mode ............................................... 36 figure 2.15 automatic bit rate matching.................................................................................. 37 figure 2.16 write control program transfer processing (1)...................................................... 38 figure 2.17 write control program transfer processing (2)...................................................... 39 figure 2.18 application program transfer processing in boot mode........................................ 40 figure 2.19 transfer processing for target erase blocks .......................................................... 42 figure 2.20 application program transfer processing in user program mode ......................... 43 figure 2.21 ramcr setting transfer processing...................................................................... 44 figure 2.22 application program transfer processing during emulation.................................. 45 figure 2.23 program/erase control program configuration...................................................... 47 figure 2.24 program/erase control program: (main) flowchart ............................................... 48 figure 2.25 target erase block area erase flowchart .............................................................. 49 figure 2.26 s-type format record receive flowchart ............................................................. 50
figure 2.27 set target erase block area flowchart .................................................................. 51 figure 2.28 flash memory erase (no. 1) flowchart .................................................................. 52 figure 2.29 flash memory erase (no. 2) flowchart .................................................................. 53 figure 2.30 prewrite flowchart .................................................................................................. 54 figure 2.31 application program write flowchart .................................................................... 56 figure 2.32 flash memory write flowchart .............................................................................. 57 figure 2.33 write to ram overlapping flash memory flowchart ........................................... 59 figure 2.34 set flash memory emulation by ram flowchart.................................................. 60 figure 3.1 user machine for on-board programming/erasure................................................ 61 figure 3.2 user machine connector attachment ..................................................................... 62 figure 3.3 reset circuit ........................................................................................................ .... 63 figure 3.4 reverse current prevention circuit......................................................................... 64 figure 3.5 sci switching circuit configuration ...................................................................... 65 figure 3.6 sci switching circuit diagram............................................................................... 67 figure 3.7 12-v detector circuit i/o characteristics ............................................................... 68 figure 3.8 reset buffer circuit configuration ......................................................................... 69 figure 3.9 reset buffer circuit diagram.................................................................................. 70 figure 4.1 user machine/adapter board and host machine connections .............................. 72 figure 4.2 jumper pin settings ................................................................................................. 7 3 figure 4.3 programming mode switch setting ........................................................................ 74 figure 4.4 programming start operation.................................................................................. 75 figure 4.5 end of programming operation .............................................................................. 76 figure 4.6 programs required for user program mode ........................................................... 77 figure 4.7 user program mode startup procedure................................................................... 78 figure 4.8 programming mode switch setting ........................................................................ 81 figure 4.9 start programming operation.................................................................................. 82 figure 4.10 end of programming operation .............................................................................. 83 figure 4.11 programming mode switch setting ........................................................................ 84 figure 4.12 transfer switch operation ...................................................................................... 85 figure 4.13 application program startup ................................................................................... 86 figure 4.14 user program mode startup by user machines reset switch .............................. 86 figure 4.15 end of programming operation .............................................................................. 87 tables table 1.1 f-ztat microcomputer features ........................................................................... 1 table 1.2 overlap area setting method for the h8/538f ram............................................. 13 table 2.1 adapter board switches, connectors, and leds.................................................... 18 table 2.2 adapter board connector pin arrangement (user interface connector p1) ........... 18 table 2.3 serial interface connector p2.................................................................................. 19 table 2.4 external power connector p3.................................................................................. 19 table 2.5 operating environment ........................................................................................... 31
table 2.6 pc i/f software ....................................................................................................... 31 table 2.7 pc i/f software configuration................................................................................ 32 table 2.8 pc i/f software transfer processing ...................................................................... 35 table 2.9 overflow cycles...................................................................................................... 5 1 table 3.1 reset buffer circuit operation ............................................................................ 71

1 section 1 f-ztat microcomputer overview 1.1 f-ztat microcomputer product introduction the f-ztat is a single-chip microcomputer with a built-in flash memory, on-board programming, and erasure capability. since the f-ztat microcomputer allows on-board programming, you can set the optimum parameters for every piece of equipment in which it is installed. the device also lets you take advantage of software upgrades after the product is shipped, making maintenance easier. there are two on-board programming modes (boot mode and user program mode) that can be set according to conditions (see section 1.2, on-board programming modes). programming and erasure are possible even with a general purpose prom writer. f-ztat microcomputers are available in the h8/500 series (h8/538f), h8/300 series (h8/3434f, h8/3334yf), and h8/300h series (h8/3048f). features of the f-ztat microcomputers are shown in table 1.1. note: f-ztat (flexible-zero turn around time) is a trademark of hitachi ltd.
2 table 1.1 f-ztat microcomputer features product item h8/538f h8/3334yf h8/3434f h8/3048f cpu h8/500 cpu h8/300 cpu h8/300h cpu max. operating frequency ? 16 mhz (5 v) ? 10 mhz (3 v) ? 16 mhz (5 v) ? 10 mhz (3 v) ? 16 mhz (5 v) ? 10 mhz (3 v) flash memory capacity (kbyte) 60 32 128 flash memory erase block partitions (blocks) 15 12 16 programming cycles 100 cycles guaranteed program/erase voltage vpp = 12 v 0.6 v programming time 50 m s/byte (typ.) erase time 1 s (typ.) program/erase method ? cpu control method (software control method) ? prom writer programming 1.2 on-board programming modes there are two on-board programming modes: boot mode for batch programming/erasure, and a user program mode that allows presetting of block areas for programming and erasure. user program mode parameters that require frequent rewriting during program development can be rewritten in real-time while tuning (flash memory emulation by ram). for more information about on-board programming modes, see the hardware manual for each f-ztat microcomputer device (on-board programming modes). 1.2.1 boot mode boot mode activates the boot program built into the f-ztat microcomputer to program and erase application programs in the on-chip flash memory. the user sets up the application and programming control program (for controlling flash memory reprogramming) in the transfer source. the f-ztat microcomputer uses an on-chip serial communication interface (sci) (channel 1, start-stop sync mode) to send the program from the transfer source.
3 the three steps below correspond to figure 1.1 to give an overview of the boot mode. 1. first, reset the f-ztat microcomputer. 2. apply 12 v to the vpp pin and mode pin, and start the boot program by canceling reset. the boot program transfers the write control program received from the transfer source to the f-ztat microcomputers on-chip ram. all areas of the on-chip flash memory are then erased. the h8/3434f and h8/3334yf boot program transfers the write control program to ram after erasure of all areas of flash memory. 3. after erasure, there is a branch from the boot program to the write control program that was transferred to the f-ztat microcomputers on-chip ram, and the application program received from the transfer source is written to flash memory. 1. f-ztat microcomputer transfer source application program write control program sci 2. 3. boot program flash memory reset state ram f-ztat microcomputer transfer source application program sci cancel reset startup f-ztat microcomputer transfer source sci boot program ram write control program boot program flash memory application program ram write control program startup 12 v to v pp pin and mode pin erase all flash memory areas figure 1.1 boot mode overview 1.2.2 user program mode in user program mode, the program/erase control program transferred in advance to the f-ztat microcomputers flash memory, and the program that transfers this program to ram (ram
4 transfer program) are written in boot mode or prom mode. figure 1.2 shows an overview of user program mode. transfer of an application from the transfer source using a hitachi on-board programming tool is via the f-ztat microcomputers built-in sci (channel 1, start-stop sync mode). the three steps below correspond to figure 1.2 to give an overview of the user program mode. 1. first, reset the f-ztat microcomputer. 2. apply 12 v to the vpp pin and start the ram transfer program by canceling reset. the program/erase program is transferred to ram (on-chip or external) and started up. 3. the program/erase control program erases block areas specified by the user, and writes the application program received from the transfer source to that area. 1. f-ztat microcomputer f-ztat microcomputer f-ztat microcomputer transfer source application program sci or parallel 2. 3. sci or parallel sci or parallel flash memory reset state ram ram transfer program transfer source application program 12 v to v pp pin reset state flash memory ram transfer source flash memory ram * ram transfer program startup program/ erase control program startup program/ erase control program application program ram transfer program program/ erase control program figure 1.2 user program mode overview figures 1.3 to 1.5 show the on-chip flash memory block partitions for each product in the f-ztat microcomputer line.
5 8 kbyte large block area (56 kbytes) h'0000 h'1fff 8 kbyte h'2000 h'3fff 8 kbyte h'4000 h'5fff 8 kbyte h'6000 h'7fff 8 kbyte h'8000 h'9fff 8 kbyte h'a000 h'bfff 8 kbyte h'c000 h'dfff h'c000 h'ee7f 1 kbyte small block area (3.6 kbytes) h'e000 h'e3ff 1 kbyte h'e400 h'e7ff 512 byte h'e800 h'e9ff 256 byte h'ea00 h'eaff 256 byte h'eb00 h'ebff 256 byte h'ec00 h'ecff 256 byte h'ed00 h'edff 128 byte h'ee00 h'ee7f figure 1.3 block partitioning of h8/538f on-chip flash memory
6 large block area (28 kbytes) h'0000 h'0fff 4 kbyte h'1000 h'1fff h'2000 8 kbyte h'3fff h'4000 8 kbyte h'5fff 8 kbyte h'6000 h'7fff 128 byte small block area (4 kbytes) h'e000 h'007f 128 byte h'0080 h'00ff 128 byte h'0100 h'017f 128 byte h'0180 h'01ff 512 byte h'0200 h'03ff 1 kbyte h'0400 h'07ff 1 kbyte h'0800 h'0bff 1 kbyte h'0c00 h'0fff figure 1.4 block partitioning of h8/3434f and h8/3334yf on-chip flash memory
7 16 kbyte large block area (124 kbyte) h'0000 h'3fff 16 kbyte h'4000 h'7fff 16 kbyte h'8000 h'bfff 16 kbyte h'c000 h'ffff 16 kbyte h'10000 h'13fff 16 kbyte h'14000 h'17fff 16 kbyte 12 kbyte h'18000 h'1bfff h'1c000 h'1efff small block area (4 kbyte) 512 byte h'1f000 h'1f1ff 512 byte h'1f200 h'1f3ff 512 byte h'1f400 h'1f5ff 512 byte h'1f600 h'1f7ff 512 byte h'1f800 h'1f9ff 512 byte h'1fa00 h'1fbff 512 byte h'1fc00 h'1fdff h'1fe00 h'1ffff h'1f000 h'1ffff 512 byte figure 1.5 block partitioning of h8/3048f on-chip flash memory 1.2.3 flash memory emulation by ram flash memory emulation by ram emulates small block areas of flash memory in the on-chip ram, allowing real-time rewriting of frequently rewritten parameters and other data during program development. this function reduces the number of data rewrite cycles to flash memory. for ram area emulation, set the control registers for each device with 12 v applied to the vpp pin. (h8/538f, h8/3048f: ram control register (ramcr) lower 4 bits; h8/3434f, h8/3334yf: wait state control register (wscr) upper 2 bits.) figures 1.6 through 1.10 give an overview of flash memory emulation by ram in the user program mode.
8 preparation for flash memory emulation by ram : first write the program/erase control program (control program for flash memory program/erase and ram area change) and the program that transfers this program to ram, to the f-ztat microcomputers built-in flash memory either in boot mode or prom mode. reset the f-ztat microcomputer (figure 1.6). reset state parameters and other data sci or parallel interface ram f-ztat microcomputer flash memory application program ram transfer program program/ erase control program transfer source figure 1.6 preparation for flash memory emulation by ram
9 user program mode startup : apply 12 v to the vpp pin to cancel reset and start up the ram transfer program and transfer the program/erase control program to on-chip or external ram for startup (figure 1.7). 12 v to v pp pin transfer source cancel reset parameters and other data sci or parallel interface ram f-ztat microcomputer flash memory application program ram transfer program program/ erase control program program/ erase control program startup figure 1.7 user program mode startup
10 program/erase control program startup: setting the ram area change register (h8/538f, h8/3048f: ramcr; h8/3434f, h8/3334yf: wscr) makes the program/erase control program emulate a flash memory area in part of the ram area. next, the f-ztat receives program data and writes it to the emulating ram area (figure 1.8). transfer source program/erase control program startup ram f-ztat microcomputer flash memory application program parameter and other data ram transfer program overlapped ram sci or parallel interface 12 v to v pp pin state program/ erase control program figure 1.8 program/erase control program startup
11 application program startup : after programming, the program/erase control program branches to the application program. after the branch, the user checks whether the application is running normally. to change data again, restart user program mode, and rewrite the required parameters and other data (figure 1.9). transfer source ram f-ztat microcomputer application program parameter and other data ram transfer program program/erase control program 12 v to v pp pin state flash memory sci or parallel interface startup figure 1.9 application program startup
12 writing to flash memory : after data confirmation, cancel ram emulation. (h8/538f, h8/3048f: ramcrs rams bit; h8/3434f, h8/3334yf: wscrs rams and ram0 bits are cleared.) data written to ram is held externally, and can be written again to flash memory in user program mode (figure 1.10). transfer source ram f-ztat microcomputer flash memory startup application program parameters and other data ram transfer program program/erase control program sci or parallel interface figure 1.10 writing to flash memory ram area change register: to emulate flash memory area in ram, set the control register for each device with 12 v applied to the vpp pin. (h8/538f, h8/3048f: ram control register (ramcr) lower 4 bits, h8/3434f, h8/3334yf: wait state control register (wscr) upper 2 bits.) setting methods for the ramcr of h8/3048f and for the wscr of h8/3434f and h8/3334yf are shown in the respective f-ztat microcomputer hardware manuals (flash memory emulation by ram). table 1.2 shows how to set the overlap area for the h8/538f ram.
13 table 1.2 overlap area setting method for the h8/538f ram bit 3 bit 2 bit 1 bit 0 rams ram2 ram1 ram0 used ram area ram overlap area 0 0/1 0/1 0/1 h'f680Ch'f6ff h'f680Ch'f6ff 1 0 0 0 h'ec00Ch'ec7f 1 0 0 1 h'ec80Ch'ecff 1 0 1 0 h'ed00Ch'ed7f 1 0 1 1 h'ed80Ch'edff 1 1 0 0 h'ee00Ch'ee7f ? bits 3C0 set a small block area of flash memory to overlap a ram area. ? bits 3C0 can be set when 12 v is applied to the vpp pin. ? the overlap ram area is 128 bytes located at addresses h'f680Ch'f6ff (figure 1.11). ? the flash memory area that can be superimposed in ram (h'ec00Ch'ee7f) is 128 bytes 5 blocks.
14 h'0000 h'ebff h'ec00 small block area (sb5) h'ec7f h'ecff h'ed00 h'ee7f h'f680 h'f6ff h'f700 h'fe7f on-chip flash memory 128 byte overlapped ram on-chip ram figure 1.11 ram overlap operation example (addresses h'ec00Ch'ecff) 1. apply 12 v to the vpp pin, and set ramcr bits 3C0 to 1, 0, 0, 0. 2. setting ramcr causes ram area addresses h'f680Ch'f6ff overlap with flash memory area addresses h'c00Ch'ecff) in ram. 3. when canceling the overlap, reset ramcr bits 3C0, and cut the 12 v to the vpp pin. notes: 1. when overlapping flash memory area in ram, it is not possible to access the overlapped flash memory area. access is resumed when you cancel overlap. 2 . ram area addresses h'f680Ch'f6ff overlapping flash memory area allow access in two areas: the flash memory overlap area and original area (addresses h'f680 to h'f6ff). 3. when the rams bit of ramcr is set to 1, all areas of flash memory are protected against programming and erasure, rendering program/erase invalid. therefore, set the rams bit to 0 for program/erase.
15 4 . for details of flash memory program/erase protection see the hardware manual of the particular f-ztat microcomputer device you are using (program/erase protect mode). 1.2.4 program voltage (vpp = 12 v) on/off, and reset signal timing for program/erase of an application program in the f-ztat microcomputers built-in flash memory, use the timing shown in figure 1.12 for vpp (12 v) on/off and reset signal control. precautions: 1. if the vcc voltage does not satisfy the rated voltage (vcc = 2.7 to 5.5 v), do not turn vpp (12 v) on/off since this could result in an erroneous program/erase operation to flash memory. 2. when applying vpp with vcc power on, apply vpp during oscillation settling time (toscl = 20 ms) after reset has been held low. 3. turn vpp on/off when the f-ztat microcomputer is reset, or when the cpu is not accessing flash memory (during execution of a program in on-chip ram or external memory space). flash memory cannot be read normally the instant vpp on/off is activated. 4. when doing a program/erase for flash memory when an f-ztat microcomputer application is running, turn vpp on/off after the reset pin has been driven low. (h8/538f: during 6 system clock cycles minimum; h8/3048f, h8/3434f, h8/3334yf: during 10 system clock cycles minimum.) 5. when programming in boot mode, apply 12 v to the mode pin with the same timing as vpp on/off.
16 f v cc 2.7 v to 5.5 v 12 v 0.6 v 2.7 v to 5.5 v v pp res 0 m s min t osc1 0 m s min h8/538f: 6 f min h8/3048f, h8/3434f: 10 f min (when res = low) : flash memory access disable and v pp flag set clear figure 1.12 program voltage (vpp = 12 v) on/off timing
17 section 2 on-board programming tools 2.1 adapter board the adapter board is the hardware supplying the required voltage for program/erase during on- board programming of an f-ztat microcomputer in a user system. figure 2.1 shows the adapter board. table 2.1 gives a description of the adapter boards switches, connectors, and leds. table 2.2 shows the boards connector pin layout. ser sp hs0008easf1h/1 sp power switch power sw gs s3 serial interface connector power supply switching jumper switch user interface connector 1 3 s1 transfer switch v pp on led (red) power led (green) programming mode switch s2 jp1 p1 mode start/ stop power vppon p2 external power supply connector p3 d3 d4 g o s + + 1 3 4 1 1 1 2 3 1 1 3 2 3 4 figure 2.1 adapter board
18 table 2.1 adapter board switches, connectors, and leds name function external power connector connects external power (vcc = 5 v) power switch controls external power supply on/off serial interface connector connects rs-232c cable from host machine power supply switching jumper switch switches power supplies between external source and user machine source user interface connector connects user machine power led (green) lights when adapter board power is on vpp on led (red) lights when vpp voltage is applied transfer switch controls on/off of 12 v voltage required for writing data to f-ztat microcomputer programming mode switch switches between f-ztat microcomputer on-board programming modes (boot mode, user program mode) table 2.2 adapter board connector pin arrangement (user interface connector p1)* 1 pin no. pin name comments 1 gnd ground connection 2 rxd receives serial data from user machine 3 txd sends serial data to user machine 4 res outputs reset signal to f-ztat microcomputer on user machine 5 vin inputs vcc (3 v to 5 v) from user machine 6 vpp applies 12 v needed for on-board programming to vpp pin 7 mode pin* 2 applies 12 v needed for on-board programming to mode pin 8 gnd ground connection notes: 1. manufacturer: koku denshi model: il-s-8p-s2l2-ef 2. mode pin: 12 v applied to mode 2 pin of h8/538f and h8/3048f (md2) and to mode 1 pin (md1) of h8/3434f and h8/3334yf.
19 table 2.3 serial interface connector p2* pin no. pin name comments 1 rxd receives serial data from host machine 2 txd sends serial data to host machine 3 gnd ground connection note: manufacturer: koku denshi; model: il-s-3p-s2l2-ef table 2.4 external power connector p3* pin no. pin name comments 1 nc not connected 2 vin inputs vcc (5 v) from external power supply 3 nc not connected 4 gnd ground connection note: manufacturer: koku denshi; model: il-s-2p-s2l2-ef 2.2 hardware configuration the adapter board (figure 2.2) is composed of: ? an rs-232c interface (a) ? switch unit (program mode switching/vcc, vpp supply on/off) (b) ? on-board programming power supply timing unit (c) ? power supply (d)
20 interface circuit with host machine reset signal control circuit delay circuit 12-v on/off circuit v cc monitor circuit 12-v power supply generator transfer switch programming mode switch adapter board 5-v power supply generator power switch power supply switching jumper switch sci user machine power supply v cc (3 v to 5 v) res pin f-ztat microcomputer v pp pin mode pin v cc pin a. 9600 bit/s host machine (ibm pc or pc-9801) 2 b. d. adapter board v cc (5 v) b. c. 9600 bit/s user machine figure 2.2 adapter board configuration sections a, b, c, and d in figure 2.2 correspond to sections 2.2.1C2.2.4.
21 2.2.1 rs-232c interface hardware specification : converts signal line voltage level (rs-232c ? cmos/ttl level) during serial communications with host machine or user system. figure 2.3 shows a circuit configuration example of the rs-232c interface section. rs-232c adapter board cmos/ttl level converter ic host machine connection rs-232c level data user machine connection cmos/ttl level data rxd p2 pin no. pin no. serial interface connector user interface connector 1 txd gnd rxd p1 txd 2 3 2 3 figure 2.3 rs-232c interface circuit configuration example
22 hardware operation : converts the signal line voltage between 12 v level ? cmos/ttl level during serial communication using an rs-232c ? cmos/ttl level converter ic. connection of adapter board to an ibm pc : use an rs-232c cable for connection to an ibm pc (figure 2.4). rxd txd sg rxd txd host machine connection serial interface connector adapter board ibm pc gnd rts cts 2 3 5 1 pin no. pin no. 2 3 7 8 p2 ibm-pc rs-232c connector figure 2.4 connecting the adapter board to an ibm pc
23 connection of adapter board to a pc-9801 : use an rs-232c cable for connection to a pc- 9801 (figure 2.5). txd rxd rts rxd txd host machine connection serial interface connector adapter board pc-9801 gnd cts gnd 2 3 4 1 pin no. pin no. 2 3 5 7 p2 pc-9801 rs-232c connector figure 2.5 example of rs-232c interface circuit configuration
24 2.2.2 switch unit (program mode switching and vcc/vpp on/off) program mode switching (s1): switches between the f-ztat microcomputers on-board programming modes: boot mode (apply 12 v to vpp pin and mode pin) and user program mode (apply 12 v to vpp pin). figure 2.6 illustrates programming mode switching. boot mode (12 v applied to v pp pin and mode pin) user program mode (12 v applied to v pp pin) mode programming mode switch s1 figure 2.6 programming mode switching
25 transfer switch (s2) : when you press the transfer switch to start programming of the f-ztat microcomputer, an led (d3) lights, and 12 v is applied. at the end of programming, press the switch again and the led (d3) goes off, and the 12-v supply is stopped. figure 2.7 shows the transfer switch. start/ stop start of programming end of programming transfer switch on s2 v pp on led (red) d3 v pp on led (red) shows 12-v supply is off shows 12-v supply is on led on led off d3 figure 2.7 transfer switch power switch (s3) : controls on/off for vcc = 5 v from external power supply (figure 2.8). power sw power switch external power supply off 2 s3 1 power sw power switch external power supply on 2 s3 1 figure 2.8 power switch
26 power supply switching jumper switch (jp1) : switches between external power supply and user machine power supply (figure 2.9). jumper setting jp1 12 34 description supplies v cc (5 v) from external power supply supplies v cc (3 v? v) from user machine power supply : short : open jp1 12 34 figure 2.9 power supply switching jumper switch
27 2.2.3 on-board programming power-on timing unit hardware specification: controls the program voltage (vpp = 12 v) on/off and reset signal output when programming/erasing application programs for the f-ztat microcomputer. figure 2.10 shows the timing control circuit configuration. a. reset signal control circuit b. delay circuit 20 ms 10 ms c. 12-v supply on/off circuit 12-v power supply generator circuit v cc monitor circuit transfer switch programming mode switch to user machine v pp pin to user machine reset pin to user machine mode pin start/ stop s2 mode s1 figure 2.10 timing control circuit configuration hardware operation : this section details aCc in figure 2.10. figure 2.11 shows an adapter board timing example. a. the reset signal control circuit holds the res pin low for 20 ms when you press the transfer switch. b. the delay circuit allows 12-v on/off for the 12-v on/off circuit 10 ms after the res pin falling edge. c. when 12-v on/off is enabled from the delay circuit, the 12-v on/off circuit conducts 12-v on/off to the f-ztat microcomputer.
28 write processing 2.7 v to 5.5 v 2.7 v to 5.5 v 12 v 10 ms 10 ms 20 ms 10 ms 10 ms 20 ms v cc v v cc v pp res figure 2.11 adapter board 12-v on/off and reset signal control timing
29 2.2.4 power unit hardware specification : generates the 12 v required for f-ztat microcomputer programming. circuit configuration : figure 2.12 shows a circuit configuration example. v cc 5-v supply to adapter board 12-v on/off circuit external power supply connector power supply switching jumper switch power switch 12 v nc vin nc gnd p3 5 v 1 12 v input reset signal to all adapter board? general logic circuits user interface connector v cc b. v cc monitor circuit 2 3 4 gnd vin gnd p3 (3 v to 5 v) 1 5 8 a. 12-v power supply generator circuit c. adapter board 5-v power supply generator circuit figure 2.12 power unit circuit configuration hardware operation : a. the 12-v power supply circuit inputs either vcc (3 vC5 v) from the user machine or vcc (5 v) from the external power supply depending on the power supply switching jumper switch setting, and generates the required 12 v for f-ztat microcomputer programming. b. applying 12 v when the f-ztat microcomputers vcc is not within 2.7 vC5.5 v could result in a faulty program/erase operation. the user machine vcc is monitored by the vcc monitor circuit, and when the voltage drops below 2.6 v (typ.) the 12-v program/erase voltage is not applied to the f-ztat microcomputer. if voltage drops below 2.6 v during a 12-v programming voltage supply, the supply is switched off. c. the adapter boards 5-v power supply circuit converts the 12 v supplied by the 12-v generator to 5 v, and supplies this voltage to the general logic vcc pin of adapter boards.
30 2.3 pc interface software pc interface software enables writing of application programs on ibm-pc* 1 or pc9801* 2 to the f-ztat microcomputers flash memory on-board the user machine. notes: 1. ibm-pc is a trademark of international business machines (u.s.a.). 2. pc-9801 is a trademark of nec (japan). 2.3.1 functions boot mode: ? sets the transfer rate (automatic bit rate matching) between the host machine and f-ztat microcomputer. ? transfers the programming control program to the f-ztat microcomputers on-chip ram. ? writes the host machine application program (s-type format) to flash memory. ? the programming control program transferred to the on-chip ram controls writing to flash memory and receiving of the application program. user program mode : ? writes the host machine application program (s-type format) to flash memory. ? selects areas of flash memory for block erase from the host machine. ? enables use of flash memory emulation by ram function from host machine. (note that this function is available in pc i/f software version 2.0 or later.) ? writes the program/erase control program from pc i/f software in advance to flash memory. the control program manages receiving of program/erase and application programs in flash memory by making ram transfers during user program mode startup. connections : connections between the user machine and host machine are shown in figure 2.13.
31 pc i/f software host machine f-ztat micro- computer rs-232c adapter board user machine figure 2.13 user machine to host machine connection operating environment and available formats : table 2.5 shows the pc i/f software operating environment. (transfer rate in boot mode is determined by the operating frequency.) table 2.5 operating environment transfer speed 9600, 4800, 2400 bps sync system start-stop sync data bit 8 stop bit 1 parity none available pc i/f software types and ms-dos versions they run under are given in table 2.6. table 2.7 shows the file organization. table 2.6 pc i/f software host machine product name development environment pc-98 hs6400fwpd2sf ms-dos (v2.11, v3.1) ibm-pc hs6400fwip2sf pc-dos (v3.1)
32 table 2.7 pc i/f software configuration f-ztat microcomputer file h8/538f h8/3434f h8/3048f f-ztat microcomputer on-board programming tool flash.exe (common) flash memory block information file h8/538f.inf h8/3434f.inf h8/3048f.inf user program/erase control program h8/538f.sub h8/3434f.sub h8/3048f.sub user program/erase control program source file h8/538f.src h8/3434f.src h8/3048f.src note: to start up pc i/f software, it is necessary to change the file names of the flash memory block information file and the users program/erase control program file. see the f-ztat microcomputer on-board programming tools section in the user manual for details. for example, when employing the h8/3048f, change the: ? h8/3048.inf filename to flash.inf ? h8/3048f.sub filename to flash.sub ? h8/3048f.src filename to flash.src 2.3.2 pc i/f software display on host machine display of pc i/f software (version 2.0) on the host machine is described in 1C4 below. 1. display on the host machine when pc i/f software is loaded is as follows: a>flash ---------------------------------------- (a) f-ztat micro computer on-board purge/write tool ver2.0 copyright(c) hitachi, ltd. 1993C1995 licensed material of hitachi, ltd. boot program mode (y/n)?------------------------ (b) description : a. start pc i/f software. b. select yes (y) for boot mode or no (n) for user program mode. 2. display on host machine during boot mode startup is as follows: boot program mode (y/n)? y----------------------------- (a) -------------- (b) charge 12 v at vpp and mode pin! (boot program mode)
33 and then release reset signal. input any key!------------------------ (key input) send the boot program to mcu--------------------------- (c) ******------------------------------------------------- (d) finish sending the user program!----------------------- (e) :w filename.mot (ret)---------------------------------- (f) transfer data address ooooxxxx------------------------- (g) : q------------------------------------------------------ (h) description : a. enter y to start up boot mode. b. the hardware setting sequence for starting the f-ztat microcomputers boot program is displayed. c. display shows automatic bit rate matching is being conducted, and that the write control program is being transferred. d. asterisks (*) are displayed while the boot program erases all areas of flash memory. e. display shows that the write control program has been sent. f. input the filename of the application program with the w command. g. display shows that application program is being sent. h. end pc i/f software with the q command. 3. display on host machine during user program mode startup is as follows: boot program mode (y/n)? n----------------------------- (a) -------------- (b) charge 12 v at vpp pin! (user program mode) baudrate (1:9600 2:4800 3:2400)----------------------- (c) input any key!------------------- (key input) :w filename.mot---------------------------------------- (d) erase block address 00000000C0000xxxx(y/n)?------------ (e) : transfer data address 0000xxxx------------------------- (f) : q --------------------------------------------------- (g)
34 description : a. enter n to start up user program mode. b. the hardware setting sequence for starting the f-ztat microcomputers user program mode is displayed. c. set the host machine transfer rate. d. input the filename of the application program with the w command. e. the application program is written. select flash memory block area erase. f. display shows that application program is being sent. g. end pc i/f software with the q command. 4. display on host machine during flash memory emulation by ram is as follows: :r--------------------------------------------- (a) ram emulation ooooxxxx ooooxxxx (y/n)?--------- (b) : : w filename.mot xxxx xxxx--------------------- (c) transfer data address ooooxxxx----------------- (d) :q -------------------------------------------- (e) description : a. input the r command for flash memory emulation by ram. b. select part of on-chip ram for overlapping with flash memory area. (since the on-chip ram area for transferring the program/erase control program with the h8/3434f and the h8/3334yf is insufficient, the r command cannot be used.) c. input the filename of the application program with the w command to capture in ram only data in the overlapped flash memory area. d. sending application program message displayed. e. end pc i/f software with the q command. 2.3.3 pc i/f software transfer processing pc i/f software (version 2.0) has the transfer processing listed in table 2.6.
35 during flash memory emulation by ram in boot mode and user program mode, pc i/f software conducts f-ztat microcomputer program/erase and flash memory emulation by ram with the transfer processing items in table 2.8. a transfer processing flowchart for each mode is shown in figure 2.14. table 2.8 pc i/f software transfer processing transfer processing control details automatic bit rate matching sets the transfer rate between host machine and f-ztat microcomputer during boot mode (h'00 continuous transfer). write control program transfer processing transfers write control program (binary data) to the f-ztat microcomputers on-chip ram. start address transfer processing for targeted block(s) transfers start address (s-type format) of each erase block for flash memory block erasure. application program transfer processing transfers application program for writing to flash memory (s-type format). ram control register (ramcr) setting transfer processing transfers ramcr settings for flash memory emulation by ram.
36 write end start transfer processing b. write control program transfer processing a. bit rate matching write end start transfer processing write end start transfer processing 1. transfer processing in boot mode 2. transfer processing in user program mode 3. transfer processing during execution of flash memory emulation by ram a.transfer ram control register (ramcr) setting a. erase blocks start address transfer processing b. application program transfer processing b. application program transfer processing c. application program transfer processing figure 2.14 transfer processing in each pc i/f software mode transfer processing in boot mode (figure 2.14, process 1) : pc i/f software transfer processing details for boot mode are described in 1C3 below. 1. automatic bit rate matching (figure 2.14, step 1a) automatic bit rate matching on the host machine is conducted only when boot mode is selected. figure 2.15 shows processing for automatic bit rate matching.
37 a. boot program startup host machine c. start automatic bit rate matching d. send automatic bit rate matching processing end sign b. continuous h'00 send e. h'00 receive h'00 h'00 f-ztat micro- computer figure 2.15 automatic bit rate matching a. apply 12 v to the f-ztat microcomputers vpp pin and mode pin to start the boot program. b. host machine sends a continuous h'00. c. the boot program measures receive data h'00 low period, and begins automatic bit rate matching (setting transfer rate).* d. at the end of automatic bit rate matching the boot program sends an end sign h'00. e. host machine receives end sign h'00 for automatic bit rate matching. note: automatic bit rate matching (transfer rate setting) is determined by the f-ztat microcomputers operating frequency. the host machine sends h'00 continuously to the f-ztat microcomputer at a transfer rate of 9600 bps, and ends automatic matching receiving an end sign h'00. if unable to receive an end sign h'00, the host machine decrements the bit rate in steps (4800 bps to 2400 bps) and continues sending until an end sign h'00 is received. if unable to receive an end sign h'00 at 2400 bps, the error message flash error-flash time-out error is displayed on the host machine. for more information, see bit rate matching in the f-ztat microcomputer hardware manual. 2. program/erase control program transfer processing (figure 2.14, step 1b):
38 write control program transfer processing is conducted after the end of automatic bit rate matching. figure 2.16 shows program/erase control program transfer processing. host machine receive transfer start sign d. send erase error sign if erase error occurs b. h8/3434f and h8/3334yf erase all flash memory areas after receiving h'55 c. h8/3048f sends h'aa after receiving h'55. h8/3434f and h8/3334yf send h'aa after erase end. a. send write control program transfer start sign receive h'aa e. receive erase error sign h'55 h'aa h'ff boot program f-ztat micro- computer figure 2.16 write control program transfer processing (1) a. the host machine sends out a start sending h'55 for the program/erase control program. b. the h8/3434f and the h8/3334yf boot program erases all areas of flash memory after receiving h'55. c. the h8/3048f boot program sends an h'aa after receiving an h'55. (the h8/538f does not send an h'aa.) the h8/538f and h8/3048f shift to program/erase control program transfer processing (2). the h8/3434f and the h8/3334yf boot program sends an h'aa after erasing all areas of flash memory. d. if the h8/3434f and the h8/3334yf boot program failed to erase flash memory correctly, the program sends an h'ff as an erase error sign.
39 e. the host machine receives an erase error sign h'ff for h8/3434f and the h8/3334yf, and displays the error message flash error-flash device error. figure 2.17 shows program/erase control program transfer processing (2). host machine g. receive write control program byte count d. j. h8/538f and h8/3048f erase all flash memory areas k. h8/3048f sends h'aa after erase end. h8/3434f and h8/3334yf send h'aa after receiving write control program. l. send erase error sign in the event of erase error n. branch to write control program f. send write control program byte count h'aa receive byte count upper i. receive write control program h. send write control program 1 byte (binary) byte count lower verify data verify data verify data h'aa m. receive error sign h'ff boot program f-ztat micro- computer figure 2.17 write control program transfer processing (2) f. the host machine sends the number of bytes of the program/erase control program in order from upper to lower bytes. g. the boot program sends verify data for the received number of bytes in byte units for each byte in sequence (echo back). h. the host machine sends the program/erase control program binary data in byte units. (note: pc i/f software converts flash.sub files (s-type format) to binary data for transfer.)
40 i. the boot program transfers the received program/erase control program to the on-chip ram, and sends verify data in sequence in byte units (echo back). j. after receiving the program/erase control program, the h8/538f and h8/3048f boot programs erase the entire flash memory area. k. after erasing the entire flash memory area, the h8/3048f boot program sends an h'aa. (the h8/538f does not send h'aa.) after receiving the program/erase control program, the h8/3434f and h8/3334yf send h'aa and shift to application program transfer processing. l. if the h8/538f or h8/3048f boot program failed to erase flash memory correctly, the program sends an h'ff as an erase error sign. m. the host machine receives an erase error sign h'ff for h8/538f and h8/3048f, and displays the error message flash error-flash device error. n. the boot program branches to the program/erase control program transferred to the on- chip ram. 3. application program transfer (figure 2.14, step 1c) application program transfer processing is done after the boot program erases flash memory. figure 2.18 shows application program transfer processing in boot mode.
41 write control program a. input application program host machine receive w c. send transmit enable sign e. receive a pplication program and write to flash memory b. send w receive transmit enable sign w application program x-on (h'11) f. request application program x-on (h'11) g. application program write end receive w rite end sign d. send application program as one record ack (h'06) h. send write error sign i. receive w rite error sign bell (h'07) f-ztat micro- computer figure 2.18 application program transfer processing in boot mode a. enter the filename of the application program you are writing to flash memory in the host machine. b. the host machine sends a w command. c. the program/erase control program sends a send enable sign x-on (h'11) and an application program transfer request to the host machine. d. the application program (s-type format) is sent as one record to the host machine. e. the program/erase control program receives the application program and writes it to flash memory. f. if the application program is not the final record (s9, s8 record), the program/erase control program sends an x-on and requests an application program transfer to the host machine. g. after programming, the program/erase control program sends a programming end sign ack (h'06). h. if a programming error occurs, the program/erase control program sends a programming error sign bell (h'07).
42 i. the host machine receives the programming error sign bell and displays the error message flash error-flash write error. transfer processing in user program mode (figure 2.14, process 2) : pc i/f software transfer processing in user program mode is described in 1 and 2 below. 1. transfer of start address of target erase blocks (figure 2.14, step 2a) transfer processing for the start address of the blocks to be erased is conducted after inputting the application program to be written to flash memory is input in the host machine and after selecting the blocks of flash memory for erasure. figure 2.19 shows transfer for start address for the objective erase blocks. a. program/erase control program startup b. input application program host machine receive w d. send transmit enable sign f. c. send w receive transmit enable sign w one record send x-on (h'11) g. x-on (h'11) i. h. receive erase end sign e. send address of blocks for erasure as one record ack (h'06) j. receive start address of blocks for erasure as one record send transmit enable sign send erase end sign erase target block area send erase error sign k. receive erase error sign bell (h'07) f-ztat micro- computer receive transmit enable sign figure 2.19 transfer processing for target erase blocks a. in user program mode the program/erase control program previously written to flash memory is transferred to on-chip ram for startup. b. enter the filename of the application program for writing to flash memory in the host machine, and select the target blocks of flash memory for erasure. c. the host machine sends a w command.
43 d. the program/erase control program sends a transfer data enable sign x-on (h'11). e. the host machine sends the start address (s-type format) of the blocks for erasure in one record. f. the program/erase control program sets the blocks for erasure from the received erase blocks start address. g. if the received erase blocks start address is not the end record (s9, s8 record), the program/erase control program sends an x-on and requests transfer of the erase blocks start address to the host machine. h. after receiving the erase blocks start address, the program/erase control program erases the areas in the objective erase blocks. i. the program/erase control program sends an ack (h'06) as an erase end sign. j. if an erase error occurs, the program/erase control program sends an erase error sign bell (h'07). k. the host machine receives the a programming error sign bell and displays the error message flash error-flash erase error. 2. application program transfer (figure 2.14, step 2b) application program transfer processing is done after flash memory erase. figure 2.20 shows application program transfer processing in user program mode.
44 host machine a. send transmit enable sign c. receive application program write to flash memory receive transmit enable sign x-on (h'11) application program d. request application program x-on (h'11) e. send application program write end receive write end sign b. send one record application program ack (h'06) f. send write error sign g. receive write error sign bell (h'07) f-ztat micro- computer program/erase control program figure 2.20 application program transfer processing in user program mode a. after sending the erase end sign, the program/erase control program sends the transmit enable sign x-on (h'11) and an application program transfer request to the host machine. b. send one application program record (s-type format). c. the program/erase program receives the application program and writes it to flash memory. d. if the application program is not the last record (s9, s8 record), the program/erase control program sends an x-on and an application program transfer request to the host machine. e. after writing, the program/erase control program sends a write end sign ack (h'06). f. if a write error occurs, the program/erase control program sends a write error sign bell (h'07). g. the host machine receives the write error sign bell, and displays an error message flash error-flash write error. transfer processing during flash memory emulation by ram (figure 2.14, process 3) : transfer processing during flash memory emulation by ram is described in 1 and 2 below.
45 1. transfer processing for ram control register (ramcr) setting (figure 2.14, step 3a) ramcr setting transfer processing is conducted after selecting flash memory emulation by ram. figure 2.21 shows ramcr setting transfer processing. program/erase control program host machine receive r b. send ack a. send r command c. send ramcr setting r ramcr setting ack (h'06) d. receive ramcr setting, set ramcr and overlap portion of on-chip ram to flash memory e. send ramcr setting end sign receive end sign ack (h'06) f-ztat micro- computer figure 2.21 ramcr setting transfer processing a. host machine sends the r command. b. after receiving the r command, the program/erase control program sends an ack. c. after receiving the ack, the host machine sends the ramcr setting for the selected overlap portion of flash memory in ram. d. the program/erase control program receives the ramcr setting and sets the ramcr. e. the program/erase control program sends an ack after setting ramcr. 2. application program transfer (figure 2.14, step 3b) application program transfer processing (during flash memory emulation by ram) is done after the end of ramcr setting transfer processing. figure 2.22 shows application program transfer processing during emulation.
46 write control program a. input application program host machine receive w c. send transmit enable sign e. receive application program and write to on-chip ram b. send w receive transmit enable sign w application program x-on (h'11) f. request application program x-on (h'11) g. send application program write end sign receive write end sign d. send application program as one record ack (h'06) h. branch to application pro g ram f-ztat micro- computer figure 2.22 application program transfer processing during emulation a. enter the filename of the application program you are writing to ram in the host machine. b. the host machine sends a w command. c. the program/erase control program sends a send enable sign x-on (h'11) and an application program transfer request to the host machine. d. host machine sends application program (s-type format) 1 record. e. the program/erase control program receives the application program and writes it to the ram area overlapping the flash memory area. f. if the application program is not the final record (s9, s8 record), the program/erase control program sends an x-on and requests application program transfer to the host machine. g. after writing, the program/erase control program sends a write end sign ack (h'06). h. the program/erase control program branches to the application program.
47 2.3.4 pc i/f software program/erase control program in boot mode, the pc i/f software program/erase control program controls transfers to the f-ztat microcomputers on-chip ram and write operations to flash memory. in user program mode, the program/erase control program prewritten to flash memory is transferred to the on-chip ram and is started to control flash memory program and erase. during flash memory emulation by ram, the program overlaps a portion of ram to flash memory area and writes the application program to the overlapped ram. figure 2.23 shows the configuration of the program/erase control program, and details of 1 through 10 in the figure are shown in the flowcharts on the following pages. the h8/3048f is cited as an example for the method of flash memory program and erase. for more information on flash memory program/erase see flash memory programming and erasure in the relevant f-ztat microcomputer hardware manual. program/erase control program (figure 2.24) target erase block area erase (figure 2.25) flash memory erase (figures 2.28 and 2.29) pre-write (figure 2.30) s-type format receive (figure 2.26) application program write (figure 2.31) set flash memory emu- lation by ram (figure 2.34) flash memory write (figure 2.32) write to ram flash memory emulation area (figure 2.33) target erase block area set (figure 2.27) s-type format receive (figure 2.26) figure 2.23 program/erase control program configuration figure 2.24 shows the management of the entire programming control program.
48 initialize sci: enable txd1 pin, rxd1 pin and enable send/receive send write end sign ack code (h'06) to host machine send write end sign ack code (h'06) to host machine erase target erase block area (erase flash memory) write application program (write to flash memory) program/erase control program: main branch to application program w received from host machine? flash memory erased? write error? yes yes no no yes no application program confirmed for flash memory emulation by ram? (ramcr? rams bit = 1?) yes no yes set flash memory emulation by ram r received from host machine? no send error sign bell code (h'07) to host machine figure 2.24 program/erase control program: (main) flowchart
49 figure 2.25 shows the management of flash memory erasure. s-type format record receive (target erase block area start address) s-type format record receive (target erase block area start address) set target erase block area erase flash memory target erase block area erase rts branch to w receive standby state s-type receive buffer has start record? (s0 record received?) yes no s-type receive buffer has end code? (s9, s8 record received?) yes no send error sign bell code (h'07) figure 2.25 target erase block area erase flowchart
50 figure 2.26 shows the s-type format record receive process. s-type format record receive branch to w receive standby state rts no no send transmit enable sign x-on code (h'11) to host machine receive s-type format (one-record receive) store receive data in s-type receive buffer (work area set in on-chip ram) send error sign bell code (h'07) to host machine s-type receive buffer address + 1 ? s-type receive buffer address yes yes one-record receive ended? (receive data = cr code h'0d) one-record receive normal? (checksum processing) figure 2.26 s-type format record receive flowchart
51 figure 2.27 shows how to set erase block registers (ebr1, ebr2) for received s-type format single record (target erase block start address). set target erase block area rts no set address section to target erase block area start address convert one-record (address section) stored in s-type receive buffer to binary data regard block area shown by target erase block area start address as the erase area and set (in bit 1 of ebr1 and ebr2) yes s-type receive buffer has end record? (s9 record received?) figure 2.27 set target erase block area flowchart figure 2.28 shows how to erase the block area (indicated by a 1 in the erase block register) and conducts erase verify. set the timers overflow cycle to the wdt overflow times listed in table 2.9. table 2.9 overflow cycles frequency value 10 mhz to 16 mhz h'a57f 2 mhz to 10 mhz h'a57f 1 mhz to 2 mhz (h8/3048f only) h'a57d
52 1 2 3 flash memory erase all erase block register bits (ebr1, ebr2) = 0? no yes : setting required for h8/3048f prewrite set erase counter n to 1 enable watchdog timer wait (x) ms* 2 disable watchdog timer set flmcr? e-bit erase mode to on set flmcr? v pp e bit wait 5?0 m s* 1 set flmcr? e-bit erase mode to off notes: 1. set with software timer 2. x = 6.25 ms 2 n C 1 (n = 1, 2, 3, 4) figure 2.28 flash memory erase (no. 1) flowchart figure 2.29 shows the flash memory erase (no. 2) process.
53 no no no no no no set flmcr? ev-bit erase verify mode to on wait 4 m s* dummy write h'ff wait 2 m s* set flmcr? ev-bit erase verify mode to off clear ebr1 and ebr2 bits corresponding to erase blocks next block erase verify set erase block start address to verify address verify (read data = h'ff?) block final address? erase all target blocks erase verify over? target erase blocks erase verify over? erase all target blocks erase over? yes yes yes yes yes yes clear flmcr? v pp e bit address + 1 ? address next block erase verify n + 1 ? n erase time = 50 ms? n 3 602? double erase time x 2 ? x erase error detected rts 1 2 3 note: h8/3434f and h8/3334yf erase time is fixed at 10 ms figure 2.29 flash memory erase (no. 2) flowchart
54 figure 2.30 shows how to write h'00 to the entire target erase block area. set flmcr? v pp e bit wait 5?0 m s* 1 set target erase block start address from ebr1 and ebr2 invert read data and write to flash memory* 2 set flmcr? p-bit to switch write mode on clear flmcr? p bit to switch write mode off set write counter to n = 1 enable watchdog timer wait (x) m s* 3 wait 4 m s* 1 read flash memory data disable watchdog timer : setting required for h8/3048f. h8/3434f, and h8/3334yf write time is fixed at 10 m s to 20 m s. prewrite 1 2 3 4 notes: 1. set with software timer 2. write with a byte transfer instruction 3. x = 15 s 2 nC1 (n = 1, 2, 3, 4, 5, 6) figure 2.30 prewrite flowchart
55 no no yes no target erase block end address? yes no target erase block prewritten? yes rts clear flmcr? v pp e bit write error detected n + 1 ? n : setting required for h8/3048f. h8/3434f and h8/3334yf write time is fixed at 10 m s to 20 m s. yes double write time x 2 ? x prewrite next block address + 1 ? address 1 2 3 4 read data = h'00? n 3 6?* 4 note: 4: do not exceed a total write time of 1 ms figure 2.30 prewrite flowchart (cont) figure 2.31 shows how to manage the application program write.
56 receive s-type format record (application program) receive s-type format record (application program) flash memory write write to ram overlapping flash memory application program write s-type receive buffer contains start record? (s0 record received?) no yes ram over- lapped with flash memory? (ramcr? rams bit = 1?) no yes write error occurred? yes no s-type receive buffer contains end record? (s9 record received?) no yes send error sign bell code (h'07) to host machine branch to standby for w receive rts figure 2.31 application program write flowchart
57 figure 2.32 shows how to convert the application program in s-type format record buffer to binary data and writes it into flash memory. set start address and end address from s-record buffer contents s-record receive buffer address + 2 ? s-record receive buffer address convert read 2-byte data to 1-byte binary data do 2-byte read of s-record receive buffer contents (s-type format data section) flash memory write s-type receive buffer contains endrecord? (s9 record?) yes no set write counter to n = 1 set flmcr? v pp e bit set specified register for erase block (set bit designating target write block to 1) wait 5 m s to 10 m s* : required setting for h8/3048f : required setting for h8/3048f, h8/3434f, and h8/3334yf 1 2 3 write binary data to flash memory figure 2.32 flash memory write flowchart
58 end address? yes yes no no clear flmcr? p-bit to switch write verify mode off set flmcr? pv-bit to switch write verify mode on clear flmcr? pv-bit to switch write verify mode off clear flmcr? pv-bit to switch write verify mode off set flmcr? p-bit to write verify mode on wait 4 m s* 1 write error detected double the write time x 2 ? x address + 1 ? address n + 1 ? n enable watchdog timer* 2 wait (x) m s* 3 rts disable watchdog timer 1 2 3 verify? (read data = write data) n 3 6? clear flmcr? v pp e bit notes: 1. set with software timer 2. set timer overflow cycle (cks2 = 0, cks1 = 0, cks0 = 1) 3. x = 15 m s 2 n C 1 (n = 1, 2, 3, 4, 5, 6) 4. setting required for h8/3434f and h8/3334yf write time is fixed at 10C20 ms 5. overwrite required for h8/538f (products before june 95) figure 2.32 flash memory write flowchart (cont)
59 figure 2.33 shows how to write the application program to the ram area emulating the flash memory area during flash memory emulation by ram. do 2-byte read of s-record receive buffer convert read 2-byte data to 1-byte binary data s record receive buffer address + 2 ? s record receive buffer address write binary data to ram? flash memory emulation write to ram flash memory emulation area rts s-type receive buffer contains final record? (s9 record?) yes no are write start and end addresses within the ram? flash memory emulation area? no yes end address? no yes write error detected set start and end addresses of ram area emulating flash memory from ramcr values set write start and end addresses from contents of s-record receive buffer write address + 1 ? write address figure 2.33 write to ram overlapping flash memory flowchart
60 figure 2.34 shows how to set flash memory emulation by ram. send ramcr setting ended sign ack code (h'06) to host machine set received value in ramcr; overlap flash memory area in portion of ram receive ram control register (ramcr) value from host machine send ack code (h'06) to host machine set flash memory emulation by ram rts figure 2.34 set flash memory emulation by ram flowchart
61 section 3 examples of use with user machine 3.1 user machine for on-board programming the type of circuitry shown in figure 3.1 is needed to conduct on-board programming/erasure for the f-ztat microcomputer in the user machine using the adapter board. parts 1C3 in figure 3.1 are described in sections 3.1.1C3.1.3. rs-232c adapter board user machine 2. reset circuit 3. reverse current protection circuit note: * h8/538f, h8/3048f: md2 pin h8/3434f, h8/3334yf: md1 pin host machine f-ztat micro- computer v pp md * res rxd1 txd1 v cc 3 v to 5v 1. user machine connector protection circuit user machine reset circuit protection circuit figure 3.1 user machine for on-board programming/erasure
62 3.1.1 user machine connector attach the adapter board to the connector on the user machine as shown in figure 3.2. connector on user machine side (manufacturer: koku denshi, model: il-s-8p-s2l2-ef) user machine *: mode pin adapter board f-ztat micro- computer v pp md* res rxd1 txd1 v pp 3 v to 5v 2 3 4 5 6 7 8 1 figure 3.2 user machine connector attachment
63 3.1.2 reset circuit connect the adapter boards reset pin to the user machine reset circuit as shown in figure 3.3. user machine adapter board f-ztat micro- computer res v cc reset pin user machine reset circuit figure 3.3 reset circuit
64 3.1.3 reverse current prevention circuit when inserting a pull-up resistor at the f-ztat microcomputers vpp pin, it is necessary to insert a diode to prevent reverse current in the vcc line when 12 v is applied from the adapter board (figure 3.4). the mode pin must also have a diode when a pull-up resistor is connected (mode pin set to 1) in order to set the microcomputers operation mode. (when conducting a pull-down to gnd (mode pin set to 0), insert the resistor and connect to gnd.) also connect a by-pass capacitor near the vpp pin. mode pin user machine adapter board f-ztat micro- computer v pp v cc v cc 0.01 m f mode pin 12 v v pp pin 12 v 1.0 m f figure 3.4 reverse current prevention circuit note: with the h8/538f and h8/3048f, the vpp pin and wdt reset output (reso) are combined. take care when using as a reset output pin, as a delay is caused in the reset output rise and fall due the effect of the pull-up resistor and by-pass capacitor connected to the vpp pin.
65 3.2 sci switching circuit example when conducting on-board programming in boot mode, the boot program loaded in the f-ztat microcomputer uses sci channel 1 (txd1, rxd1) to interface with the host machine. employing sci1 with the user system therefore requires an sci1 switching circuit in the user machine. if you use sci1 in user program mode, and employ pc i/f software and the adapter board, an sci1 switching circuit is also required. the sci switching circuit is detailed in sections 3.2.1 and 3.2.2. 3.2.1 sci switching circuit configuration figure 3.5 shows the sci switching circuit configuration. during on-board programming, the circuit detects 12 v applied to the vpp pin and switches from user system sci to the programming sci. at the end of a programming operation, the absence of 12 v at the vpp pin is detected, and the circuit switches back from the programming sci to user system sci. rxd1 txd1 f-ztat micro- computer txd1 v pp 12-v detector circuit sci switching circuit user machine rxd1 v pp sci switching signal programming sci user system sci adapter board connector figure 3.5 sci switching circuit configuration
66 3.2.2 sci switching circuit operation hardware specification : ? detects 12 v applied to the vpp pin during on-board programming. ? on detecting 12 v, outputs sci switching circuit switching signal. ? sci switching circuit inputs switching signal to switch scis. circuit diagram : figure 3.6 shows the sci switching circuit operating at vcc = 5 v. the vcc monitor ciruit and 12 v detection circuit are sample circuits based on vcc= 5 v. if used with vcc less than 5 v, therefore, the circuits will need to be revised. if the h8/538f or h8/3048f vpp pin is not used as the reso pin by the user system, when the sci switching circuit in the circuit example shown in figure 3-6 is configured, the vpp pin should be connected to the 12 v detection circuit. (the vcc monitor circuit need not be connected.)
67 user system sci txd1 f-ztat micro- computer v pp v pp rxd1 v cc v cc v cc switching signal switching signal 4.7 k w 20 k w hz6hc1 2sa673ak 1.0 m f 0.01 m f 4.7 k w 4.7 k w switching circuit v cc monitor circuit 12-v detector circuit hc126 hc125 txd1 rxd1 hc125 hc126 10 k w 3.3 k w v cc v cc v pp input 41 k w ha17901 3.3 k w 10 k w 16 k w 30 k w + + 20 k w 20 k w ha17901 3.3 k w figure 3.6 sci switching circuit diagram
68 hardware operation : ? the vcc monitoring circuit outputs vpp voltage to the 12-v detector circuit when 12 v is applied (approx. 6.5 v) to the vpp pin. ? the 12-v detector circuit senses 12 v applied to the vpp pin (approx. 10.9 v) and outputs a low level switching signal to the sci switching circuit. when a voltage of about 7.6 v or less is detected, the circuit outputs a high level switching signal to the sci switching circuit. figure 3.7 shows the input/output characteristics of the 12-v detector circuit. 12 v on (high to low switching) switching signal output (v) switching signal output (v) v pp pin voltage (v) 5 3 024681012 12 v on (low to high switching) v pp pin voltage (v) 5 3 024681012 figure 3.7 12-v detector circuit i/o characteristics ? the sci switching circuit inputs a switching signal from the 12-v detector circuit, and switches to the user system sci if the level is high, and to the programming sci if the level is low.
69 3.3 reset buffer circuit example the reset buffer circuit switches between the signal from the reset switch in the user machine and the reset signal input from the adapter board during on-board programming. figure 3.8 shows the reset buffer circuit configuration. f-ztat micro- computer res res adapter board connector reset buffer circuit user reset circuit user reset sw user machine figure 3.8 reset buffer circuit configuration
70 3.3.1 reset buffer circuit operation hardware specification : switches between reset signal from the adapter board and the user system reset signal. figure 3.9 shows the circuit diagram. res user power-on reset circuit v cc v cc reset buffer circuit user reset switch user machine f-ztat micro- computer res adapter board connector figure 3.9 reset buffer circuit diagram
71 hardware operation : the reset buffer circuit inputs a reset signal from the adapter board and switches the f-ztat microcomputers reset pin high and low by switching the base of the transistor (2sci213) on/off (table 3.1). table 3.1 reset buffer circuit operation adapter board reset signal input hc04 output transistor on/off f-ztat reset pin high low off high low high on low high impedance* low off high note: when adapter board and user machine are not connected.
72 section 4 on-board programming methods 4.1 on-board programming methods this section details the operation method when writing application programs to the f-ztat microcomputer in the user system employing boot mode and user program mode. for more information on the operation method for the adapter board and pc i/f software see the relevant user manual. 4.1.1 on-board programming preparation connect the user machine and adapter board, and the host machine. see section 3.1, user machine for on-board programming, for the connection method for the user machine and adapter board. f-ztat micro- computer rs-232c host machine adapter board user machine figure 4.1 user machine/adapter board and host machine connections set the adapter board jumper pin to supply power to the adapter board either from the user side or from the 5-v (dc) supply. when supplying power from the 5-v (dc) connect to the 5-v (dc) connector on the adapter board.
73 jumper pin setting jp1 12 34 description supplies v cc (5 v) from external power supply supplies v cc (3 v to 5 v) from user machine jp1 12 34 : open : short figure 4.2 jumper pin settings note: when you supply power to the adapter board from the user machine, note that the adapter boards current consumption is 500 ma (5-v supply) and 900 ma (3-v supply). be sure to check the capacity of the power supplied. 4.1.2 programming in boot mode programming in boot mode is described in steps 1C7 below. you will need the adapter board and pc i/f software (version 2.0). 1. connect the user machine and adapter board and host machine. see section 4.1.1, on-board programming preparation, for user machine/adapter board details. 2. switch on the user machine power. when supplying adapter board power from an external source, switch on the adapter board power switch. the adapter boards power on led will light (green). 3. set the adapter boards mode switch to boot mode (figure 4.3).
74 boot mode mode figure 4.3 programming mode switch setting 4. start the pc i/f software on the host machine. the pc i/f software operation method (1) for boot mode is shown below: a>flash (ret) ---------------------------------- (a) f-ztat micro computer on-board purge/write tool ver2.0 copyright(c) hitachi, ltd. 1993C1995 licensed material of hitachi, ltd. boot program mode (y/n)? y-------------------- (b) ------- (c) charge 12 v at vpp and mode pin! (boot program mode) and then release reset signal. input any key! description: a. start up pc i/f software. b. enter y for boot mode. c. the hardware setting sequence for boot mode startup is displayed. 5. press the adapter boards transfer switch to apply 12 v to the vpp and mode pins. when 12 v is applied the adapter boards vpp on led lights (red). the f-ztat microcomputer starts the boot program.
75 v pp on led (red) when 12 v supplied start/ stop figure 4.4 programming start operation 6. operate pc i/f software from the host machine. the pc i/f software operations (2) for boot mode is shown below: input any key!--------------------------- (a) send the boot program to mcu------------- (b) ****************************------------- (c) finish sending the user program!--------- (d) : w filename.mot------------------------- (e) transfer data address ooooxxxx----------- (f) : q (ret)------------------ (g) description: a. input any key. b. display shows that automatic bit rate matching for the f-ztat microcomputer is under way and that the program/erase control program is being sent. c. a string of asterisks (*) is displayed while the boot program erases all areas of flash memory. d. display shows that transfer of the program/erase control program to the f-ztat microcomputer is complete. e. input the application program filename using the w command. f. display shows that the application program is being transferred. g. end pc i/f software with the q command.
76 7. press the adapter boards transfer switch to stop the 12-v supply to the vpp pin and mode pin. the vpp on led (red) goes off. the f-ztat microcomputer in the user machine starts the application program. start/ stop v pp on led 12 v supply stopped figure 4.5 end of programming operation 4.1.3 user program mode preparation preparation for user program mode with pc i/f software (version 2.0) is described in steps 1C4 below. 1. programs required for user program mode the programs shown in figure 4.6 are needed for user program mode. first write these programs with the prom writer in boot mode as part of the application program. processing in each of the programs listed in figure 4.6 is described in figure 4.7.
77 f-ztat microcomputer user machine on-chip flash memory a. application program : programs required for user program mode (write as part of the application program) b. v pp flag detection program c. rams bit detection program d. ram transfer program e. program/erase control program note: programs required for user program (write as part of the application program). figure 4.6 programs required for user program mode description: a. application program: controls the user system (program the user creates) b. vpp flag detection program: detect the vpp flag in the flash memory control register (flmcr) (vpp = 12 v) created by user. c. rams bit detection program: detects rams bit in the ram control register (ramcr) signifying that the flash memory emulation by ram application program is running. (created by user.) this is not required when not using flash memory emulation by ram. note that pc i/f software cannot be used with the h8/3434 and h8/3334yf in flash memory emulation by ram since the ram area for transfer of the program/erase control program is too small. d. ram transfer program: transfers the program/erase control program to ram during user program mode startup (created by user). e. program/erase control program: controls receiving of application programs operating in ram and write/erase to flash memory during user program mode (program controlling write/erase operations of pc i/f software). 2. user program mode startup procedure: figure 4.7 shows this procedure.
78 user program mode startup user program mode end application program run user program mode execution procedure end 12 v to v pp pin off 12 v to v pp pin on no no yes yes no yes b. rams bit = 1? d. flash memory write/ erase processing flash memory emulation by ram running? : processing by v pp flag detection program : processing by rams bit detection program : processing by ram transfer program : processing by program/erase control program c. program/erase control program transfer processing a. v pp flag = 1? figure 4.7 user program mode startup procedure
79 description: a. the vpp flag detection program detects the vpp flag in the flash memory control register (flmcr). user program mode is started up when the vpp flag = 1 (vpp pin = 12 v). b. the rams bit detection program detects the rams bit in the ram control register (ramcr). if the rams bit = 1, the application program to check parameters and other data in flash memory emulation by ram is started up. (in the case of h8/3434f and h8/3334yf, it is necessary to perform a logical or on the rams bit and ram0 bit in addition to checking the rams bit.) note that this is only required during flash memory emulation by ram. pc i/f software cannot be used with the h8/3434f and h8/3334yf in flash memory emulation by ram since the ram area for transfer of the program/erase control program is too small. c. the ram transfer program transfers the pc i/f software program/erase control program written in flash memory to ram. after transfer, the program/erase control program in ram is started up. the pc i/f software program/erase control program operates in the f-ztat microcomputers on-chip ram area (ram area for transfer of the program/erase control program during boot mode). when transferring the program/erase control program to the ram area during user program mode, transfer to the on-chip ram area (e.g., when operation mode = 7, operation is at ram area addresses h'ff300 to h'fff0f.) d. the program/erase control program erases the flash memory block area to which you are writing the application program, receives the application program from the host machine, and writes it to flash memory. when running flash memory emulation by ram, the control program overlaps a portion of ram to flash memory (ramcr setting), writes the application program received from the host machine, and then starts up the application program. 3. transfer rate setting in user program mode, set the f-ztat microcomputer transfer rate (sci ch1) with the ram transfer program or program/erase control program. the host machine can be set to 9600, 4800, and 2400 bps. 4. writing program/erase control program to flash memory the write address for the pc i/f software program/erase control program is fixed in the f-ztat microcomputers on-chip ram area (in boot mode, the ram area for transfer of the program/erase control program). therefore, when writing the program/erase control program to flash memory with pc i/f software, it is necessary to specify an offset (change the write address to an address in flash memory). the following is a description of how to write to flash
80 memory the program/erase control program for the h8/3048f. with the h8/3048f (operation mode = 7), the write address of the on-chip ram area is h'ff300 to h'fff0f. for details of the write method in boot mode, please refer to section 4.1.2, programming method in boot mode. boot program mode (y/n)? y charge 12 v at vpp and mode pin! (boot program mode) and then release reset signal. input any key! send the boot program to mcu **************************** finish sending the user program! :w user.mot (ret)------------------------- (a) transfer data address 0000xxxx :o fff20700 (ret)------------------------- (b) :w flash.sub (ret)------------------------ (c) transfer data address 0000xxxx :q---------------------------------------- (d) description: a. input the filename of the application program with the w command. b. specify the write address offset with the o command. in this case the program/erase control program write address changes to flash memory address h'1fa00. specify the offset 32-bit hexadecimal code. example:h'000ff300 + offset = h'0001fa00 offset = h'0001fa00 to h'000ff300 = h'fff20700 (2s complement) c. enter the program/erase control program filename with the w command. d. end pc i/f software operation with the q command.
81 4.1.4 programming in user program mode programming in user program mode is described in steps 1C7 below. you will need the adapter board and pc i/f software (version 2.0). 1. connect the user machine and adapter board and host machine. see section 4.1.1, on-board programming preparation, for user machine to adapter connection board details. 2. switch on the user machine power. when supplying adapter board power from an external source, switch on the adapter board power switch. the adapter boards power on led will light (green). 3. set the adapter boards mode switch to user program mode (figure 4.8). user program mode mode figure 4.8 programming mode switch setting 4. start the pc i/f software on the host machine. the pc i/f software operation method (1) for user program mode is as follows: a>flash (ret) ---------------------------------- (a) f-ztat micro computer on-board purge/write tool ver2.0 copyright(c) hitachi, ltd. 1993C1995 licensed material of hitachi, ltd. boot program mode (y/n)? n-------------------- (b) ------- (c) charge 12 v at vpp and mode pin! (user program mode) input any key!
82 description: a. start up pc i/f software. b. enter no (n) to select user program mode. c. the hardware setting sequence for user program mode startup is displayed. 5. press the adapter boards transfer switch to supply 12 v to the vpp pin. the adapter boards vpp on led (red) lights at this time. the f-ztat microcomputer goes into user program mode (figure 4.9). v pp on led (red) indicates 12-v supply to v pp pin start/ stop figure 4.9 start programming operation 6. operate pc i/f software on the host machine. the pc i/f software operation method in user program mode (2) is as follows: baudrate (1:9600 2:4800 3:2400) 1------------- (a) input any key!--------------------------------- (b) : w filename.mot------------------------------- (c) erase block address 00000000C00003fff(y/n)?y--- (d) : : transfer data address 0000xxxx----------------- (e) : q ------------------------------------------- (f)
83 description: a. set the host machine transfer rate. in this case the transfer rate is 9600 bps. b. enter any key. the host machine goes to command input state. c. enter the filename of the application program with the w command. d. enter y. select erase for the flash memory block area you want to write the application program to. during user program mode, the flash memory is erased by the program/erase control program. e. a sending application program message is displayed. f. end pc i/f software operation with the q command. 7. press the adapter boards transfer switch to stop the 12-v supply to the vpp pin and mode pin. the vpp on led (red) goes off (figure 4.10). the f-ztat microcomputer in the user machine starts the application program. start/ stop v pp on led 12-v supply stopped figure 4.10 end of programming operation 4.1.5 operation method for flash memory emulation by ram the operation method for flash memory emulation by ram in user program mode is described in 1C10 below, using h8/3048 as an example. you will need the adapter board and pc i/f software (version 2.0). 1. connect the user machine and adapter board and host machine. see section 4.1.1, on-board programming preparation, for user machine to adapter connection board details.
84 2. switch on the user machine power. when supplying adapter board power from an external source, switch on the adapter board power switch. the adapter boards power on led will light (green). 3. set the adapter boards mode switch to user program mode (figure 4.11). user program mode mode figure 4.11 programming mode switch setting 4. start the pc i/f software on the host machine. the pc i/f software operation method (1) for flash memory emulation by ram is as follows: a>flash (ret) ---------------------------------- (a) f-ztat micro computer on-board purge/write tool ver2.0 copyright(c) hitachi, ltd. 1993C1995 licensed material of hitachi, ltd. boot program mode (y/n)? n-------------------- (b) ------- (c) charge 12 v at vpp pin! (user program mode) input any key! description: a. start up pc i/f software. b. enter n to select user program mode. c. the hardware setting sequence for user program mode startup is displayed. 5. press the adapter boards transfer switch to supply 12 v to the vpp pin. the adapter boards vpp on led (red) lights at this time (figure 4.12). the f-ztat microcomputer goes into user program mode.
85 v pp on led (red) indicates 12-v supply to v pp pin start/ stop figure 4.12 transfer switch operation 6. operate pc i/f software on the host machine. the pc i/f software operation method in flash memory emulation by ram (2) is as follows: baudrate (1:9600 2:4600 3:2400) ?1 (ret)------------ (a) input any key!--------------------------------------- (b) : r (ret)-------------------------------------------- (c) ram emulation 0001f000 0001f1ff (y/n) ?y------------- (d) : w filename.mot 1f000 1f1ff (ret)------------------- (e) transfer data address 0000xxxx----------------------- (f) : description: a. set the host machine transfer rate. in this case the transfer rate is 9600 bps. b. enter any key. the host machine goes to command input state. c. overlap flash memory and portion of ram with the r command. d. input y to overlap flash memory area addresses h'1f000Ch'1f1ff in a portion of ram (h8/3048f sets ramcr). e. enter the application program with the w command, and write data to addresses h'1f000Ch'f1ff. (note: during flash memory emulation by ram, data write is only valid for the flash memory area overlapping the ram portion.) f. a sending application program is displayed sent to addresses h'1f000Ch'f1ff. the write operation takes up a portion of the overlapped ram.
86 7. the f-ztat microcomputer in the user machine starts the application program when the vpp pin has 12 v supplied to it (figure 4.13). host machine f-ztat micro- computer rs-232c oscilloscope logic analyzer adapter board user machine (12 v supplied to v pp pin) figure 4.13 application program startup 8. when changing or fixing data, and writing overlapping ram contents to flash memory, reset the f-ztat microcomputer in the user machine (with the user machines reset switch) and write in user program mode. ramcr is initialized with reset signal input and cancels ram overlap (figure 4.14). host machine f-ztat micro- computer reset on rs-232c adapter board user machine (12 v supplied to v pp pin) figure 4.14 user program mode startup by user machines reset switch
87 9. in flash memory emulation by ram, when rewriting data, perform step 6 above. when writing overlapping ram contents to flash memory, operate pc i/f software as follows: : r (ret) ------------------------------------------- (a) : w filename.mot 1f000 1f1ff (ret)-------------------- (b) erase block address 0001f000C0001f1ff(y/n)?y---------- (c) : : transfer data address 0000xxxx------------------------ (d) : q -------------------------------------------------- (e) description: a. cancel flash memory emulation by ram. b. enter the application program with the w command, and write to addresses h'1f000 to h'1f1ff. c. enter y. select flash memory block area erase for the application program write operation. the program/erase control program erases the specified block area of flash memory. d. the sending application program is displayed. e. end pc i/f software operation with the q command. 10. press the adapter boards transfer switch to stop the 12-v supply to the vpp pin and mode pin. the vpp on led (red) goes off (figure 4.15). the f-ztat microcomputer in the user machine starts the application program. start/ stop v pp on led indicates 12-v supply to v pp has been stopped figure 4.15 end of programming operation

f-ztat microcomputer on-board programming application note publication date: 1st edition, august 1995 published by: semiconductor and ic div. hitachi, ltd. edited by: technical document center hitachi microcomputer system ltd. co py ri g ht ? hitachi, ltd., 1995. all ri g hts reserved. printed in ja p an.

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